# This is a BitKeeper generated patch for the following project: # Project Name: Linux kernel tree # This patch format is intended for GNU patch command version 2.5 or higher. # This patch includes the following deltas: # ChangeSet 1.1348+1.1296.77.15 -> 1.1349 # include/asm-ppc64/processor.h 1.33 -> 1.34 # include/linux/sched.h 1.151.1.22 -> 1.163 # kernel/fork.c 1.132 -> 1.133 # kernel/sys.c 1.52 -> 1.53 # include/asm-ppc64/thread_info.h 1.7.1.2 -> 1.10 # arch/i386/kernel/traps.c 1.52.1.11 -> 1.59 # include/linux/nfs_fs.h 1.49 -> 1.50 # arch/ppc64/kernel/irq.c 1.30.1.6 -> 1.34 # arch/ppc64/kernel/head.S 1.39 -> 1.40 # arch/ppc64/mm/init.c 1.53 -> 1.54 # drivers/char/agp/i460-agp.c 1.25.1.4 -> 1.31 # arch/ppc64/kernel/pci_dma.c 1.16.1.1 -> 1.18 # Makefile 1.410.1.26 -> 1.423 # arch/ppc64/mm/numa.c 1.10 -> 1.11 # arch/ppc64/kernel/sys_ppc32.c 1.66.1.5 -> 1.69 # kernel/module.c 1.93 -> 1.94 # arch/ppc64/kernel/pacaData.c 1.7.1.2 -> 1.11 # mm/slab.c 1.93.1.16 -> 1.101 # kernel/sched.c 1.193.1.28 -> 1.204 # kernel/timer.c 1.59.1.12 -> 1.69 # arch/ppc64/kernel/misc.S 1.62.1.2 -> 1.64 # include/asm-ppc64/pgtable.h 1.23.1.3 -> 1.26 # include/asm-ppc64/io.h 1.8.1.1 -> 1.11 # sound/oss/cs4281/cs4281m.c 1.21.1.6 -> 1.26 # diff -Nru a/arch/ppc64/kernel/head.S b/arch/ppc64/kernel/head.S --- a/arch/ppc64/kernel/head.S Tue Oct 21 00:40:01 2003 +++ b/arch/ppc64/kernel/head.S Tue Oct 21 00:40:01 2003 @@ -937,7 +937,6 @@ mfspr r20,SPRG2 mfspr r21,SPRG1 rfid -_TRACEBACK(do_stab_bolted) /* * r20 points to the PACA, r21 to the exception frame, @@ -1052,7 +1051,6 @@ mfspr r20,SPRG2 mfspr r21,SPRG1 rfid -_TRACEBACK(do_slb_bolted) _GLOBAL(do_stab_SI) mflr r21 /* Save LR in r21 */ diff -Nru a/arch/ppc64/mm/init.c b/arch/ppc64/mm/init.c --- a/arch/ppc64/mm/init.c Tue Oct 21 00:40:01 2003 +++ b/arch/ppc64/mm/init.c Tue Oct 21 00:40:01 2003 @@ -726,3 +726,22 @@ __hash_page(ea, pte_val(pte) & (_PAGE_USER|_PAGE_RW), vsid, ptep, 0x300, local); } + +kmem_cache_t *zero_cache; + +static void zero_ctor(void *pte, kmem_cache_t *cache, unsigned long flags) +{ + memset(pte, 0, PAGE_SIZE); +} + +void pgtable_cache_init(void) +{ + zero_cache = kmem_cache_create("zero", + PAGE_SIZE, + 0, + SLAB_HWCACHE_ALIGN | SLAB_MUST_HWCACHE_ALIGN, + zero_ctor, + NULL); + if (!zero_cache) + panic("pgtable_cache_init(): could not create zero_cache!\n"); +} diff -Nru a/arch/ppc64/mm/numa.c b/arch/ppc64/mm/numa.c --- a/arch/ppc64/mm/numa.c Tue Oct 21 00:40:01 2003 +++ b/arch/ppc64/mm/numa.c Tue Oct 21 00:40:01 2003 @@ -13,6 +13,7 @@ #include #include #include +#include #include #if 1 @@ -306,6 +307,7 @@ { unsigned long zones_size[MAX_NR_ZONES]; int i, nid; + struct page *node_mem_map; for (i = 1; i < MAX_NR_ZONES; i++) zones_size[i] = 0; @@ -314,16 +316,24 @@ unsigned long start_pfn; unsigned long end_pfn; - if (node_data[nid].node_spanned_pages == 0) - continue; - start_pfn = plat_node_bdata[nid].node_boot_start >> PAGE_SHIFT; end_pfn = plat_node_bdata[nid].node_low_pfn; zones_size[ZONE_DMA] = end_pfn - start_pfn; dbg("free_area_init node %d %lx %lx\n", nid, zones_size[ZONE_DMA], start_pfn); - free_area_init_node(nid, NODE_DATA(nid), NULL, zones_size, - start_pfn, NULL); + + /* + * Give this empty node a dummy struct page to avoid + * us from trying to allocate a node local mem_map + * in free_area_init_node (which will fail). + */ + if (!node_data[nid].node_spanned_pages) + node_mem_map = alloc_bootmem(sizeof(struct page)); + else + node_mem_map = NULL; + + free_area_init_node(nid, NODE_DATA(nid), node_mem_map, + zones_size, start_pfn, NULL); } } diff -Nru a/include/asm-ppc64/processor.h b/include/asm-ppc64/processor.h --- a/include/asm-ppc64/processor.h Tue Oct 21 00:40:01 2003 +++ b/include/asm-ppc64/processor.h Tue Oct 21 00:40:01 2003 @@ -128,14 +128,6 @@ #define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */ #define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */ #define SPRN_DAR 0x013 /* Data Address Register */ -#define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */ -#define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */ -#define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */ -#define SPRN_DBAT1U 0x21A /* Data BAT 1 Upper Register */ -#define SPRN_DBAT2L 0x21D /* Data BAT 2 Lower Register */ -#define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */ -#define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */ -#define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */ #define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */ #define DBCR_EDM 0x80000000 #define DBCR_IDM 0x40000000 @@ -229,14 +221,6 @@ #define SPRN_TST 0x3FC /* Thread switch timeout */ #define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */ #define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */ -#define SPRN_IBAT0L 0x211 /* Instruction BAT 0 Lower Register */ -#define SPRN_IBAT0U 0x210 /* Instruction BAT 0 Upper Register */ -#define SPRN_IBAT1L 0x213 /* Instruction BAT 1 Lower Register */ -#define SPRN_IBAT1U 0x212 /* Instruction BAT 1 Upper Register */ -#define SPRN_IBAT2L 0x215 /* Instruction BAT 2 Lower Register */ -#define SPRN_IBAT2U 0x214 /* Instruction BAT 2 Upper Register */ -#define SPRN_IBAT3L 0x217 /* Instruction BAT 3 Lower Register */ -#define SPRN_IBAT3U 0x216 /* Instruction BAT 3 Upper Register */ #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ #define ICCR_NOCACHE 0 /* Noncacheable */ #define ICCR_CACHE 1 /* Cacheable */ @@ -333,14 +317,6 @@ #define CTR SPRN_CTR /* Counter Register */ #define DAR SPRN_DAR /* Data Address Register */ #define DABR SPRN_DABR /* Data Address Breakpoint Register */ -#define DBAT0L SPRN_DBAT0L /* Data BAT 0 Lower Register */ -#define DBAT0U SPRN_DBAT0U /* Data BAT 0 Upper Register */ -#define DBAT1L SPRN_DBAT1L /* Data BAT 1 Lower Register */ -#define DBAT1U SPRN_DBAT1U /* Data BAT 1 Upper Register */ -#define DBAT2L SPRN_DBAT2L /* Data BAT 2 Lower Register */ -#define DBAT2U SPRN_DBAT2U /* Data BAT 2 Upper Register */ -#define DBAT3L SPRN_DBAT3L /* Data BAT 3 Lower Register */ -#define DBAT3U SPRN_DBAT3U /* Data BAT 3 Upper Register */ #define DCMP SPRN_DCMP /* Data TLB Compare Register */ #define DEC SPRN_DEC /* Decrement Register */ #define DMISS SPRN_DMISS /* Data TLB Miss Register */ @@ -354,14 +330,6 @@ #define TSC SPRN_TSC /* Thread switch control */ #define TST SPRN_TST /* Thread switch timeout */ #define IABR SPRN_IABR /* Instruction Address Breakpoint Register */ -#define IBAT0L SPRN_IBAT0L /* Instruction BAT 0 Lower Register */ -#define IBAT0U SPRN_IBAT0U /* Instruction BAT 0 Upper Register */ -#define IBAT1L SPRN_IBAT1L /* Instruction BAT 1 Lower Register */ -#define IBAT1U SPRN_IBAT1U /* Instruction BAT 1 Upper Register */ -#define IBAT2L SPRN_IBAT2L /* Instruction BAT 2 Lower Register */ -#define IBAT2U SPRN_IBAT2U /* Instruction BAT 2 Upper Register */ -#define IBAT3L SPRN_IBAT3L /* Instruction BAT 3 Lower Register */ -#define IBAT3U SPRN_IBAT3U /* Instruction BAT 3 Upper Register */ #define ICMP SPRN_ICMP /* Instruction TLB Compare Register */ #define IMISS SPRN_IMISS /* Instruction TLB Miss Register */ #define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */ @@ -391,84 +359,6 @@ #define THRM3 SPRN_THRM3 /* Thermal Management Register 3 */ #define XER SPRN_XER - -/* Device Control Registers */ - -#define DCRN_BEAR 0x090 /* Bus Error Address Register */ -#define DCRN_BESR 0x091 /* Bus Error Syndrome Register */ -#define BESR_DSES 0x80000000 /* Data-Side Error Status */ -#define BESR_DMES 0x40000000 /* DMA Error Status */ -#define BESR_RWS 0x20000000 /* Read/Write Status */ -#define BESR_ETMASK 0x1C000000 /* Error Type */ -#define ET_PROT 0 -#define ET_PARITY 1 -#define ET_NCFG 2 -#define ET_BUSERR 4 -#define ET_BUSTO 6 -#define DCRN_DMACC0 0x0C4 /* DMA Chained Count Register 0 */ -#define DCRN_DMACC1 0x0CC /* DMA Chained Count Register 1 */ -#define DCRN_DMACC2 0x0D4 /* DMA Chained Count Register 2 */ -#define DCRN_DMACC3 0x0DC /* DMA Chained Count Register 3 */ -#define DCRN_DMACR0 0x0C0 /* DMA Channel Control Register 0 */ -#define DCRN_DMACR1 0x0C8 /* DMA Channel Control Register 1 */ -#define DCRN_DMACR2 0x0D0 /* DMA Channel Control Register 2 */ -#define DCRN_DMACR3 0x0D8 /* DMA Channel Control Register 3 */ -#define DCRN_DMACT0 0x0C1 /* DMA Count Register 0 */ -#define DCRN_DMACT1 0x0C9 /* DMA Count Register 1 */ -#define DCRN_DMACT2 0x0D1 /* DMA Count Register 2 */ -#define DCRN_DMACT3 0x0D9 /* DMA Count Register 3 */ -#define DCRN_DMADA0 0x0C2 /* DMA Destination Address Register 0 */ -#define DCRN_DMADA1 0x0CA /* DMA Destination Address Register 1 */ -#define DCRN_DMADA2 0x0D2 /* DMA Destination Address Register 2 */ -#define DCRN_DMADA3 0x0DA /* DMA Destination Address Register 3 */ -#define DCRN_DMASA0 0x0C3 /* DMA Source Address Register 0 */ -#define DCRN_DMASA1 0x0CB /* DMA Source Address Register 1 */ -#define DCRN_DMASA2 0x0D3 /* DMA Source Address Register 2 */ -#define DCRN_DMASA3 0x0DB /* DMA Source Address Register 3 */ -#define DCRN_DMASR 0x0E0 /* DMA Status Register */ -#define DCRN_EXIER 0x042 /* External Interrupt Enable Register */ -#define EXIER_CIE 0x80000000 /* Critical Interrupt Enable */ -#define EXIER_SRIE 0x08000000 /* Serial Port Rx Int. Enable */ -#define EXIER_STIE 0x04000000 /* Serial Port Tx Int. Enable */ -#define EXIER_JRIE 0x02000000 /* JTAG Serial Port Rx Int. Enable */ -#define EXIER_JTIE 0x01000000 /* JTAG Serial Port Tx Int. Enable */ -#define EXIER_D0IE 0x00800000 /* DMA Channel 0 Interrupt Enable */ -#define EXIER_D1IE 0x00400000 /* DMA Channel 1 Interrupt Enable */ -#define EXIER_D2IE 0x00200000 /* DMA Channel 2 Interrupt Enable */ -#define EXIER_D3IE 0x00100000 /* DMA Channel 3 Interrupt Enable */ -#define EXIER_E0IE 0x00000010 /* External Interrupt 0 Enable */ -#define EXIER_E1IE 0x00000008 /* External Interrupt 1 Enable */ -#define EXIER_E2IE 0x00000004 /* External Interrupt 2 Enable */ -#define EXIER_E3IE 0x00000002 /* External Interrupt 3 Enable */ -#define EXIER_E4IE 0x00000001 /* External Interrupt 4 Enable */ -#define DCRN_EXISR 0x040 /* External Interrupt Status Register */ -#define DCRN_IOCR 0x0A0 /* Input/Output Configuration Register */ -#define IOCR_E0TE 0x80000000 -#define IOCR_E0LP 0x40000000 -#define IOCR_E1TE 0x20000000 -#define IOCR_E1LP 0x10000000 -#define IOCR_E2TE 0x08000000 -#define IOCR_E2LP 0x04000000 -#define IOCR_E3TE 0x02000000 -#define IOCR_E3LP 0x01000000 -#define IOCR_E4TE 0x00800000 -#define IOCR_E4LP 0x00400000 -#define IOCR_EDT 0x00080000 -#define IOCR_SOR 0x00040000 -#define IOCR_EDO 0x00008000 -#define IOCR_2XC 0x00004000 -#define IOCR_ATC 0x00002000 -#define IOCR_SPD 0x00001000 -#define IOCR_BEM 0x00000800 -#define IOCR_PTD 0x00000400 -#define IOCR_ARE 0x00000080 -#define IOCR_DRC 0x00000020 -#define IOCR_RDM(x) (((x) & 0x3) << 3) -#define IOCR_TCS 0x00000004 -#define IOCR_SCS 0x00000002 -#define IOCR_SPC 0x00000001 - - /* Processor Version Register (PVR) field extraction */ #define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */ @@ -499,26 +389,6 @@ #define XGLUE(a,b) a##b #define GLUE(a,b) XGLUE(a,b) -/* - * Begining of traceback info work for asm functions. - */ -#define TB_ASM 0x000C000000000000 -#define TB_GLOBALLINK 0x0000800000000000 -#define TB_IS_EPROL 0x0000400000000000 -#define TB_HAS_TBOFF 0x0000200000000000 -#define TB_INT_PROC 0x0000100000000000 -#define TB_HAS_CTL 0x0000080000000000 -#define TB_TOCLESS 0x0000040000000000 -#define TB_FP_PRESENT 0x0000020000000000 -#define TB_LOG_ABORT 0x0000010000000000 -#define TB_INT_HNDL 0x0000008000000000 -#define TB_NAME_PRESENT 0x0000004000000000 -#define TB_SAVES_CR 0x0000000200000000 -#define TB_SAVES_LR 0x0000000100000000 -#define TB_STORES_BC 0x0000000080000000 -#define TB_PARMINFO 0x000000000000FFFF -#define TB_DEFAULT TB_ASM | TB_HAS_TBOFF | TB_NAME_PRESENT - #ifdef __ASSEMBLY__ #define _GLOBAL(name) \ @@ -546,16 +416,6 @@ .previous; \ .type GLUE(.,name),@function; \ GLUE(.,name): - -#define _TRACEBACK(NAME) \ -GLUE(.LT,NAME): ;\ - .long 0 ;\ - .llong TB_DEFAULT ;\ - .long GLUE(.LT,NAME)-GLUE(.,NAME) ;\ - .short GLUE(GLUE(.LT,NAME),_procname_end)-GLUE(GLUE(.LT,NAME),_procname_start) ;\ -GLUE(GLUE(.LT,NAME),_procname_start): ;\ - .ascii __stringify(NAME) ;\ -GLUE(GLUE(.LT,NAME),_procname_end): #endif /* __ASSEMBLY__ */ diff -Nru a/include/linux/nfs_fs.h b/include/linux/nfs_fs.h --- a/include/linux/nfs_fs.h Tue Oct 21 00:40:01 2003 +++ b/include/linux/nfs_fs.h Tue Oct 21 00:40:01 2003 @@ -264,7 +264,7 @@ /* * linux/fs/nfs/direct.c */ -extern int nfs_direct_IO(int, struct file *, const struct iovec *, loff_t, +extern int nfs_direct_IO(int, struct kiocb *, const struct iovec *, loff_t, unsigned long); /* diff -Nru a/kernel/fork.c b/kernel/fork.c --- a/kernel/fork.c Tue Oct 21 00:40:01 2003 +++ b/kernel/fork.c Tue Oct 21 00:40:01 2003 @@ -743,12 +743,6 @@ sig->curr_target = NULL; init_sigpending(&sig->shared_pending); - sig->tty = process_tty(current); - sig->pgrp = process_group(current); - sig->session = process_session(current); - sig->leader = 0; /* session leadership doesn't inherit */ - sig->tty_old_pgrp = 0; - return 0; } @@ -795,9 +789,7 @@ * Thread groups must share signals as well, and detached threads * can only be started up within the thread group. */ - if ((clone_flags & CLONE_THREAD) && - (clone_flags & (CLONE_SIGHAND|CLONE_DETACHED)) != - (CLONE_SIGHAND|CLONE_DETACHED)) + if ((clone_flags & CLONE_THREAD) && !(clone_flags & CLONE_SIGHAND)) return ERR_PTR(-EINVAL); /* @@ -902,6 +894,8 @@ init_timer(&p->real_timer); p->real_timer.data = (unsigned long) p; + p->leader = 0; /* session leadership doesn't inherit */ + p->tty_old_pgrp = 0; p->utime = p->stime = 0; p->cutime = p->cstime = 0; p->array = NULL; @@ -1046,7 +1040,7 @@ if (thread_group_leader(p)) { attach_pid(p, PIDTYPE_TGID, p->tgid); attach_pid(p, PIDTYPE_PGID, process_group(p)); - attach_pid(p, PIDTYPE_SID, process_session(p)); + attach_pid(p, PIDTYPE_SID, p->session); if (p->pid) __get_cpu_var(process_counts)++; } else diff -Nru a/kernel/module.c b/kernel/module.c --- a/kernel/module.c Tue Oct 21 00:40:01 2003 +++ b/kernel/module.c Tue Oct 21 00:40:01 2003 @@ -485,6 +485,7 @@ set_cpus_allowed(current, cpumask_of_cpu((int)(long)cpu)); /* Ack: we are alive */ + mb(); /* Theoretically the ack = 0 might not be on this CPU yet. */ atomic_inc(&stopref_thread_ack); /* Simple state machine */ @@ -493,11 +494,13 @@ local_irq_disable(); irqs_disabled = 1; /* Ack: irqs disabled. */ + mb(); /* Must read state first. */ atomic_inc(&stopref_thread_ack); } else if (stopref_state == STOPREF_PREPARE && !prepared) { /* Everyone is in place, hold CPU. */ preempt_disable(); prepared = 1; + mb(); /* Must read state first. */ atomic_inc(&stopref_thread_ack); } if (irqs_disabled || prepared) @@ -507,6 +510,7 @@ } /* Ack: we are exiting. */ + mb(); /* Must read state first. */ atomic_inc(&stopref_thread_ack); if (irqs_disabled) diff -Nru a/kernel/sys.c b/kernel/sys.c --- a/kernel/sys.c Tue Oct 21 00:40:01 2003 +++ b/kernel/sys.c Tue Oct 21 00:40:01 2003 @@ -969,7 +969,7 @@ if (p->parent == current || p->real_parent == current) { err = -EPERM; - if (process_session(p) != process_session(current)) + if (p->session != current->session) goto out; err = -EACCES; if (p->did_exec) @@ -981,7 +981,7 @@ } err = -EPERM; - if (process_session_leader(p)) + if (p->leader) goto out; if (pgid != pid) { @@ -990,7 +990,7 @@ struct list_head *l; for_each_task_pid(pgid, PIDTYPE_PGID, p, l, pid) - if (process_session(p) == process_session(current)) + if (p->session == current->session) goto ok_pgid; goto out; } @@ -1002,7 +1002,7 @@ if (process_group(p) != pgid) { detach_pid(p, PIDTYPE_PGID); - p->signal->pgrp = pgid; + p->group_leader->__pgrp = pgid; attach_pid(p, PIDTYPE_PGID, pgid); } @@ -1044,7 +1044,7 @@ asmlinkage long sys_getsid(pid_t pid) { if (!pid) { - return process_session(current); + return current->session; } else { int retval; struct task_struct *p; @@ -1056,7 +1056,7 @@ if(p) { retval = security_task_getsid(p); if (!retval) - retval = process_session(p); + retval = p->session; } read_unlock(&tasklist_lock); return retval; @@ -1077,10 +1077,10 @@ if (pid) goto out; - current->signal->leader = 1; + current->leader = 1; __set_special_pids(current->pid, current->pid); - current->signal->tty = NULL; - current->signal->tty_old_pgrp = 0; + current->tty = NULL; + current->tty_old_pgrp = 0; err = process_group(current); out: write_unlock_irq(&tasklist_lock);